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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13604-2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16L MB90660A Series
MB90662A/663A/P663A
s DESCRIPTION
MB90660A series microcontrollers are 16-bit microcontrollers optimized for high speed realtime processing of consumer equipment and system control of air conditioner video cameras, VCRs, and copiers. Based on the F2MC*-16 CPU core, an F2MC-16L is used as the CPU. This CPU includes high-level language-support instructions and robust task switching instructions, and additional addressing modes. Microcontrollers in this series have built-in peripheral resources including multi-function timers, 16-bit reload timer four channels, 8-bit PWM one channel, UART one channel, 10-bit A/D eight converter channels, and external interrupt eight channels. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* F2MC-16L CPU * Minimum execution time: 62.5 ns/4 MHz oscillation (uses PLL multiplier): fastest speed at quadruple operation * Instruction set optimized for controller applications Upward compatibility at object level with the F2MC-16(H) Various data types (bit, byte, word, long-word) Higher speed due to review of instruction cycle Expanded addressing modes: 23 types High coding efficiency Two access methods (bank system or linear pointer) Improved multiply-and-divide instructions (additional signed instructions) Improved high-precision operation with 32-bit accumulator Extended intelligent I/O services (access area extended by 64 Kbytes) Large memory space: 16 Mbytes (Continued)
s PACKAGE
64-pin Plastic SH-DIP 64-pin Plastic LQFP
(DIP-64P-M01)
(FPT-64P-M09)
MB90660A Series
(Continued) * Improved instruction set applicable to high-level language (C) and multitasking System stack pointer Improved indirect instructions using various pointers Barrel shift instruction Stack check function * Improved execution speed: 4-byte instruction queue * Improved interrupt functions * Automatic data transfer function independent of CPU
Peripheral Resources * ROM: 16 Kbytes (MB90661A) 32 Kbytes (MB90662A) 48 Kbytes (MB90663A) One-time PROM: 48 Kbytes (MB90P663A) * RAM: 512 bytes (MB90661A) 1.64 Kbytes (MB90662A) 2 Kbytes (MB90663A/MB90P663A) * General-purpose ports: Max. 51 * UART: 1 channel Can be used for both asynchronous transfer and clocked serial (I/O extended serial) communications * A/D converter: 10-bit, 8 channels Includes 8-bit conversion mode * 16-bit reload timer: 4 channels * 8-bit PWM: 1 channel * External interrupts: 8 channels * 18-bit timebase timer with watchdog timer function * PLL clock multiplier function * CPU intermittent operation function * Various standby modes * Package: SH-DIP-64/LQFP-64 (0.65-mm pitch) * CMOS technology
2
MB90660A Series
s PRODUCT LINEUP
Part number Parameter
MB90P663A OTPROM 48 Kbytes 2 Kbytes Number of basic instructions Instruction bit length Instruction length Data bit length Minimum execution time Interrupt processing time Input Ports I/O ports (CMOS) I/O ports (N channel open-drain) Total DIP-64P-M01 FPT-64P-M09
MB90662A MASK ROM 32 Kbytes 1.64 Kbytes : 340 : 8/16 bits : 1 to 7 bytes : 1, 4, 8, 16, or 32 bits : 62.5 ns/4 MHz (PLL 4 multiply) : 1000 ns/16 MHz (minimum) :4 : 39 :8 : 51 DIP-64P-M01 FPT-64P-M09
MB90663A MASK ROM 48 Kbytes 2 Kbytes
Classification ROM size RAM size CPU functions
Ports
Packages Multi-Function Timer UART
DIP-64P-M01 FPT-64P-M09
14-bit up/down count timer x 1, buffered compare register x 4, buffered compare clear register, zero detect terminal control, 4 output channels, non-overlapped 3-phase waveform output, 3-phase independent dead time timer, 4-bit carrier counter Full duplex double buffer Selectable clock synchronous/asynchronous operation Built-in dedicated baud rate generator (During asynchronous operation: 62500, 31250, 19230, 9615, 4808, 2404, 1202 bps) 10-bit precision x 8 channels A/D conversion time Startup trigger Activiation : 6.13 s (98 machine cycles at 16 MHz machine clock, includes sample hold time) : Startup by software, external source, or multi-function timer output (RT0) can be selected : Single, scan (multiple channel continuous), continuous (1 channel continuous), stop (synchronized with conversion start in scan mode)
A/D Converter
16-Bit Reload Timer
16-bit reload timer operation (toggle output, one-shot output selectable) (Count clock can be selected from 0.125 s, 0.5 s, or 2.0 s at 16 MHz machine cycle) Event count function selectable 4 channels built-in 8-bit resolution PWM operation (arbitrary cycle: duty ratio pulse output) (Count clock can be selected from 0.125 s or 64.0 s at 16 MHz machine cycle)
8-Bit PWM
External Interrupts Number of inputs: 8 External interrupt mode (Interrupts can be generated by four types of request detect sources) PLL Function Miscellaneous Items 1/2/3/4-time multiplier can be selected (Please set so as not to exceed guaranteed operation frequency) VPP is shared with MD2 terminal (when writing the EPROM) -- --
3
MB90660A Series
s PIN ASSIGNMENT
(TOP VIEW)
P66/RT0 DTTI P40/SIN P41/SOT P42/SCK P43/PWM P44/INT0 P45/INT1 P46/INT2/TRG P47/INT3/ATG P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P30 P31 P32 P33 MD0 RST MD1 MD2 X0 X1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VCC P65/Z P64/Y P63/X P62/RT3/W P61/RT2/V P60/RT1/U VSS P27/TIM3/INT7 P26/TIM2/INT6 P25/TIM1/INT5 P24/TIM0/INT4 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00
(DIP-64P-M01)
4
MB90660A Series
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P45/INT1 P44/INT0 P43/PWM P42/SCK P41/SOT P40/SIN DTTI P66/RT0 VCC P65/Z P64/Y P63/X P62/RT3/W P61/RT2/V P60/RT1/U VSS
P46/INT2/TRG P47/INT3/ATG P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 AVCC AVR AVSS P30 P31 P32
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P27/TIM3/INT7 P26/TIM2/INT6 P25/TIM1/INT5 P24/TIM0/INT4 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10
P33 MD0 RST MD1 MD2 X0 X1 VSS P00 P01 P02 P03 P04 P05 P06 P07
(FPT-64P-M09)
5
MB90660A Series
s PIN DESCRIPTION
Pin no. SH-DIP* 30 31 33 to 40 41 to 48 49 to 52 53 to 56
1
LQFP* 22 23
2
Pin name X0 X1
Circuit type A
(Oscillator)
Function Crystal oscillator pin (32 MHz). General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports. This function is activated when the output specification of the reload timer is "disabled". I/O pins for reload timers 0 to 4. Input is used only as necessary while serving as input for the reload timer. It is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. Their function as output terminals for the reload timer is activated when the output specification is "enabled". External interrupt request input pins. Input is used only as necessary while external interrupts are enabled. It is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise.
25 to 32 P00 to P07 33 to 40 P10 to P17 41 to 44 P20 to P23 45 to 48 P24 to P27
B (CMOS) B (CMOS) B (CMOS) G (CMOS)
TIM0 to TIM3
INT4 to INT7
22 to 25 3
14 to 17 P30 to P33 59 P40 SIN
B (CMOS) E
(CMOS/H)
General-purpose I/O ports. General-purpose I/O port. This function is always enabled. UART serial data input pin. Input is used only as necessary while serving as UART input. It is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise.
4
60
P41
E
(CMOS/H)
General-purpose I/O port. This function is activated when the serial data output specification of the UART is "disabled". UART serial data output pin. This function is activated when the serial data output specification of the UART is "enabled".
SOT
*1: DIP-64P-M01 *2: FPT-64P-M09
(Continued)
6
MB90660A Series
Pin no. SH-DIP*1 5 LQFP*2 61
Pin name P42
Circuit type E
(CMOS/H)
Function General-purpose I/O port. This function is activated when the clock output specification of the UART is "disabled". UART clock I/O pin. This function is activated when the clock output specification of the UART is "enabled". Input is used only as necessary while serving as UART input. It is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise.
SCK
6
62
P43
E
(CMOS/H)
General-purpose I/O port. This function is activated when the output specification of the PWM is "disabled". PWM timer output pin. This function is activated when the waveform output specification of the PWM timer is "enabled".
PWM
7 8
63 64
P44 to P45 INT0 to INT1
D
(CMOS/H)
General-purpose I/O ports. This function is always active. External interrupt request input pins. Input is used only as necessary while external interrupts are enabled.
9
1
P46 INT2
D
(CMOS/H)
General-purpose input port. This function is always active. External interrupt request input pin. Input is used only as necessary while external interrupts are enabled. Timer clear trigger input pin for multi-function timer. Input is used only as necessary while multi-function timer input is enabled.
TRG
10
2
P47 INT3
D
(CMOS/H)
General-purpose input port. This function is always active. External interrupt request input pin. Input is used only as necessary while external interrupts are enabled. Trigger input pin for the A/D converter. Input is used only as necessary while the A/D converter is performing input.
ATG
11 to 18
3 to 10
P50 to P57
C (AD)
Open-drain type I/O ports. This function is enabled when the analog input enable register specification is "port". Analog input pins for the A/D converter. This function is enabled when the analog input enable register specification is "AD".
AN0 to AN7
*1: DIP-64P-M01 *2: FPT-64P-M09
(Continued)
7
MB90660A Series
Pin no. SH-DIP*1 58 LQFP*2 50
Pin name P60
Circuit type E
(CMOS/H)
Function General-purpose I/O port. This function is enabled when the multi-function timer waveform output specification is "disabled" and the 3-phase waveform output specification is "disabled". Multi-function timer waveform output pin. This function is enabled when the multi-function timer output specification is "enabled". 3-phase waveform output pin. This function is enabled when the 3-phase waveform output specification is "enabled".
RT1
U
59
51
P61
E
(CMOS/H)
General-purpose I/O port. This function is enabled when the multi-function timer waveform output specification is "disabled" and the 3-phase waveform output specification is "disabled". Multi-function timer waveform output pin. This function is enabled when the multi-function timer output specification is "enabled". 3-phase waveform output pin. This function is enabled when the 3-phase waveform output specification is "enabled".
RT2
V
60
52
P62
E
(CMOS/H)
General-purpose I/O port. This function is enabled when the multi-function timer waveform output specification is "disabled" and the 3-phase waveform output specification is "disabled". Multi-function timer waveform output pin. This function is enabled when the multi-function timer output specification is "enabled". 3-phase waveform output pin. This function is enabled when the 3-phase waveform output specification is "enabled".
RT3
W
61
53
P63
E
(CMOS/H)
General-purpose I/O port. This function is enabled when the 3-phase waveform output specification is "disabled". 3-phase waveform output pin. This function is enabled when the 3-phase waveform output specification is "enabled".
X
62
54
P64
E
(CMOS/H)
General-purpose I/O port. This function is enabled when the 3-phase waveform output specification is "disabled". 3-phase waveform output pin. This function is enabled when the 3-phase waveform output specification is "enabled".
Y
*1: DIP-64P-M01 *2: FPT-64P-M09
(Continued)
8
MB90660A Series
(Continued)
Pin no. SH-DIP*1 63 LQFP*2 55 Pin name P65 Circuit type E
(CMOS/H)
Function General-purpose I/O port. This function is enabled when the 3-phase waveform output specification is "disabled". 3-phase waveform output pin. This function is enabled when the 3-phase waveform output specification is "enabled".
Z
1
57
P66
E
(CMOS/H)
General-purpose I/O port. This function is enabled when the multi-function timer waveform output specification is "disabled". Multi-function timer waveform output pin. This function is enabled when the multi-function timer output specification is "enabled".
RT0
2 19
58 11
DTTI AVCC
D
(CMOS/H)
3-phase waveform output disable input (DTTI) pin. Power supply for analog circuits. Turn this power supply on/off by applying a voltage level greater than AVCC to VCC. Reference power supply for analog circuits. Turn this pin on/off by applying a voltage level greater than AVR to AVCC. Ground level for analog circuits. Input pins for specifying operation mode. Use these pins by directly connecting to VCC or VSS. External reset request input pin. Power supply for digital circuits. Ground level for digital circuits.
Power supply Power supply Power supply F
(CMOS/H)
20
12
AVR
21 26 28 29 27 64 32 57
13 18 20 21 19 56 24 49
AVSS MD0 to MD2
RST VCC VSS
D
(CMOS/H)
Power supply Power supply
*1: DIP-64P-M01 *2: FPT-64P-M09
9
MB90660A Series
s I/O CIRCUIT TYPE
Type A
X1 Clock input X0
Circuit
Remarks * 3 MHz to 32 MHz operation * Oscillation feedback resistor: Approx. 1 M3/4
Standby control signal
B
Digital output
* CMOS level input and output With standby control * Pull-up option can be selected With standby control
Digital output
Standby control signal
Digital input
C
* N-channel open-drain output CMOS level hysteresis input With A/D control
Digital output A/D input Digital input A/D disable
D
* CMOS level hysteresis input Without standby control * Pull-up option can be selected Without standby control
Digital input
(Continued)
10
MB90660A Series
(Continued)
Type E Circuit Remarks * CMOS level output * CMOS level hysteresis input With standby control * Pull-up option can be selected With standby control
Digital output
Digital output
Standby control signal
Digital input
F
*2
*3
*1
Noise filter Typ. 40 ns
Digital input
* CMOS level input (Mask ROM version uses CMOS hysteresis input) Without standby control * Pull-up option can be selected for MD2 (*1) Pull-up option can be selected for MD1/0 (*2) Both without standby option * The MB90P663A does not include a noise filter. It also does not have a P channel protect Tr (*3) for the MD2 pin or pull-down.
G
Digital output
* CMOS level input and output Without standby control * Pull-up option can be selected With standby control
Digital output
Digital input
11
MB90660A Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur with CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. To prevent the similar aftereffects, use also the utmost care not to allow the analog supply voltage to exceed the digital supply voltage.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be pins should be connected to a pullup or pull-down resistor.
3. External Reset Input
When resetting by inputting "L" level to the RST pin, the "L" level must be input for at least 5 machine cycles to ensure that internal reset has occurred. Be aware of this point when using external clock input.
4. VCC, VSS Pin
Be sure that both VCC and VSS are at the same voltage.
5. Notes on Using an External Clock
Drive X0 when using an external clock. * Using an External Clock
MB90660A X0
X1
6. Order of Power-on to A/D Converter and Analog Inputs
Power-off (AVCC, AVR) to the digital power supply (VCC) must be performed only after the A/D converter and the analog inputs (AN0 to AN7) has been turned on. Turning on or off should always be performed keeping AVR below AVCC. Use caution for the input voltage not to exceed AVCC when the pin sharing the analog input for its function is used as an input port.
7. Programming Mode
When the MB90P663A is shipped from Fujitsu, all bits (48 K x 8 bits) are set to "1". Program by setting selected bits to "0" when you wish to set the data. Note that "1" cannot be programming electrically. 12
MB90660A Series
8. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program and verify
Aging 150C, 48 H
Data verification
Assembly
9. Programming Yields
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
10.Fluctuations in Supply Voltage
Although the assured VCC supply voltage operating range is as specified, sudden fluctuations even within this range may cause a malfunction. Therefore, the voltage supply to the IC should be kept as constant as possible. The VCC ripple (P-P value) at the supply frequency (50 to 60 Hz) should be less than 10% of the typical VCC value, or the coefficient of excessive variation should not be more than 0.1 V/ms instantaneous change when power is supplied.
13
MB90660A Series
s PROGRAMMING THE MB90P663A EPROM
Since the MB90P663A is functionally equivalent to the MBM27C1000 when it is in EPROM mode, it is possible to program them with a general-purpose EPROM programmer by using a special adaptor socket. However, the MB90660A does not support the electronic signature (device ID code) mode.
1. Pin Assignment in EPROM Mode
* MBM27C1000-compatible pins MBM27C1000 Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name VPP OE A15 A12 A07 A06 A05 A04 A03 A02 A01 A00 D00 D01 D02 GND MB90P663A Pin no.
SH-DIP LQFP
MBM27C1000 Pin no. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Pin name VCC PGM NC A14 A13 A08 A09 A11 A16 A10 CE D07 D06 D05 D04 D03
MB90P663A Pin no.
SH-DIP LQFP
Pin name MD2 (VPP) P32 P17 P14 P27 P26 P25 P24 P23 P22 P21 P20 P00 P01 P02 --
Pin name VCC P33 -- P16 P15 P10 P11 P13 P30 P12 P31 P07 P06 P05 P04 P03
29 24 48 45 56 55 54 53 52 51 50 49 33 34 35 --
21 16 40 37 48 47 46 45 44 43 42 41 25 26 27 --
64 25 -- 47 46 41 42 44 22 43 23 40 39 38 37 36
56 17 -- 39 38 33 34 36 14 35 15 32 31 30 29 28
* Power supply, GND connection pins Type Power GND Pin no. SH-DIP 2 64 57 21 27 32 26 3 4 5 LQFP 58 56 49 13 19 24 18 59 60 61 Pin name DTTI VCC VSS AVSS RST VSS MD0 P40 P41 P42
14
MB90660A Series
* Pins other than MBM27C1000-compatible pins Pin no. SH-DIP 30 28 31 9 10 11 to 18 19 20 58 to 63 1 6 to 8 LQFP 22 20 23 1 2 3 to 10 11 12 50 to 55 57 62 to 64 Pin name X0 MD1 X1 P46 P47 P50 to P57 AVCC AVR P60 to P65 P66 P43 to P45 Processing Pull-up by 4.7 K OPEN
1 M-level pull-up resistor connected to each pin
2. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Compatible socket adapter Sun Hayato Co., Ltd. Recommended programmer manufacturer and programmer name Minato Electronics Inc. Recommended Recommended Data I/O Co., Ltd. Recommended Recommended Advantest Corp. Recommended Recommended
Part no.
Package
MB90P663AP MB90P663APF
SH-DIP-64 ROM-64SD-32DP-16L LQFP-64 ROM-64SF-32DP-16L
Inquiry: Sun Hayato Co., Ltd.: TEL (81)-3-3986-0403 FAX (81)-3-5396-9106 Minato Electronics Inc.: TEL: USA (1)-916-348-6066 JAPAN (81)-45-591-5611 Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444 EUROPE (49)-8-985-8580 Advantest Corp.: TEL: Except JAPAN (81)-3-3930-4111
15
MB90660A Series
3. Programming Data
(1) Adjust the EPROM programmer to settings for the MBM27C1000. (2) Load program data from addresses 10000H to 1FFFFH in the EPROM programmer. OTPROM addresses FF4000H to FFFFFFH of the MB90P663A in operation mode correspond to addresses 14000H to 1FFFFH in EPROM mode.
Operation mode FFFFFFH 1FFFFH EPROM mode
OTPROM
OTPROM
FF4000H
14000H
FF0000H
10000H
(3) Set the MB90P663A into the adaptor socket and install the adaptor socket into the EPROM programmer. Pay attention to the orientation of the device and the adaptor socket at this time. (4) Programming data to the EPROM. (5) If data cannot be programmed, try again with a 0.1 F capacitor connected between VCC and GND and VPP and GND. Note: Since Mask ROM products (MB90662A/663A) do not include an EPROM mode, data cannot be read-out using an EPROM programmer.
16
MB90660A Series
4. PROM Option Bitmap
The programming method is the same as a PROM, and can be set by programming values to addresses indicated in the memory map. The following bit map shows the relation between bits and options. * PROM Option Bitmap
Address Bit
7 P07 Pull-up 1: No 0: Yes P17 Pull-up 1: No 0: Yes P27 Pull-up 1: No 0: Yes P43 Pull-up 1: No 0: Yes
6 P06 Pull-up 1: No 0: Yes P16 Pull-up 1: No 0: Yes P26 Pull-up 1: No 0: Yes P42 Pull-up 1: No 0: Yes P46 Pull-up 1: No 0: Yes P66 Pull-up 1: No 0: Yes
5 P05 Pull-up 1: No 0: Yes P15 Pull-up 1: No 0: Yes P25 Pull-up 1: No 0: Yes P41 Pull-up 1: No 0: Yes P45 Pull-up 1: No 0: Yes P65 Pull-up 1: No 0: Yes
4 P04 Pull-up 1: No 0: Yes P14 Pull-up 1: No 0: Yes P24 Pull-up 1: No 0: Yes P40 Pull-up 1: No 0: Yes P44 Pull-up 1: No 0: Yes P64 Pull-up 1: No 0: Yes
3 P03 Pull-up 1: No 0: Yes P13 Pull-up 1: No 0: Yes P23 Pull-up 1: No 0: Yes P33 Pull-up 1: No 0: Yes RST Pull-up 1: No 0: Yes P63 Pull-up 1: No 0: Yes
2 P02 Pull-up 1: No 0: Yes P12 Pull-up 1: No 0: Yes P22 Pull-up 1: No 0: Yes P32 Pull-up 1: No 0: Yes DTTI Pull-up 1: No 0: Yes P62 Pull-up 1: No 0: Yes
1 P01 Pull-up 1: No 0: Yes P11 Pull-up 1: No 0: Yes P21 Pull-up 1: No 0: Yes P31 Pull-up 1: No 0: Yes
Accept asynchronous reset
0 P00 Pull-up 1: No 0: Yes P10 Pull-up 1: No 0: Yes P20 Pull-up 1: No 0: Yes P30 Pull-up 1: No 0: Yes MD1/MD0*2 Pull-up 1: No 0: Yes P60 Pull-up 1: No 0: Yes
00004H
00008H
0000CH
00010H
00014H *1 P47 Pull-up 1: No 0: Yes 00018H Open
1: Yes 0: No P61 Pull-up 1: No 0: Yes
Initially (value when blank), all bits are "1". *1: Under this release, the pull-up resistor is cut-off during stop mode for pins for which the pull-up option was selected. (Pins for which the circuit type shown in the "s Pin Description" is B or E.) However, the pull-up resistor is not cut-off even in stop mode for P44 to 47, RST, DTTI (pins for which the circuit type shown in the "s Pin Description" is D or G), and MD1 and MD0. *2: Whether or not a pull-up/pull-down resistor is present for MD2, MD1 and MD0 is determined as follows. If pullup/pull-down resistor is selected, it is included with all 2 (or 3) pins. Presence or absence of the pull-up or pulldown resistors for the mode terminal cannot be selected for each pin. Pin MB90P663A MB90663A/2A MD2 MD1 MD0 No With pull-up resistor With pull-up resistor Pull-down can be selected With pull-up resistor With pull-up resistor
Notes: * "FFH" must be set to addresses no defined in the table above. * Since the option setting for the MB90P663A takes 8 machine cycles, the option setting is not made until a clock is provided after power-on. (This results in no pull-up for all pins, and asynchronous reset input is accepted.) 17
MB90660A Series
s BLOCK DIAGRAM
X0, X1 RST MD0 to MD2
Clock controller
CPU F2MC-16L family core
RAM
External interrupts
INT0 to INT7
Interrupt controller ROM
F2MC-16 bus
SIN SOT SCK
UART
Multi-function timer (Dead time timer)
TRG DTTI RT0 to RT3 U, V, W X, Y, Z
AVcc AVR AVss AN0 to AN7 ATG
10-bit A/D converter
16-bit timer
TIM0 to TIM3
8-bit PWM
PWM
I/O ports 8 P00 to P07 8 P10 to P17 8 P20 to P27 4 P30 to P33 8 P40 to P47 8 P50 to P57 7 P60 to P66
Note: In the diagram above, I/O ports share pins with all internal function blocks. These cannot be used as I/O ports when used as internal module pins.
18
MB90660A Series
s F2MC-16L CPU PROGRAMMING MODEL
* Dedicated Registers
AH
AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8 bits 16 bits 32 bits
Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General-purpose Registers
32 banks max.
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4 RL1
RW2 RW1 RL0 000180H + RP 10H RW0 16 bits
* Processor States (PS)
ILM RP -- I S T N CCR Z V C
19
MB90660A Series
s MEMORY MAP
FFFFFF H
Single chip
ROM area Address1#
FF0000 H
010000 H ROM area (FF bank image) Address2#
004000 H 002000 H Address3# 000380 H RAM 000180 H 000100 H 0000C0 H Peripheral resources 000000 H : Access disabled : Internal Registers
Product Model MB90662A MB90663A MB90P663A
Address #1 FF8000H FF4000H FF4000H
Address #2 008000H 004000H 004000H
Address #3 000780H 000900H 000900H
20
MB90660A Series
s I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register/ Port data buffer register Name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6/ PDBR -- DDR0 DDR1 DDR2 DDR3 DDR4 ADER DDR6 -- -- PWMC -- PRLL PRLH SMR SCR SIDR/ SODR SSR ENIR EIRR ELVR ADCS Access*2 R/W* R/W* R/W* R/W* R/W! R/W* R/W* *1 R/W R/W R/W R/W R/W R/W R/W *1 *1 R/W *1 R/W R/W R/W! R/W! R/W R/W! R/W R/W R/W R/W! External interrupt External interrupt UART PWM Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 -- -- Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 -- Initial value XXXXXXXX XXXXXXXX XXXXXXXX - - - - XXXX XXXXXXXX 11111111 - XXXXXXX -- 00000000 00000000 00000000 ----0000 ----0000 11111111 -0000000 -- -- 00000--1 -- XXXXXXXX XXXXXXXX 00000-00 00000100 XXXXXXXX 00001-00 00000000 XXXXXXXX 00000000 00000000 A/D converter 00000000 00000000
000007H to Vacancy 0FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H to 1BH 00001CH to 1FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH 00002CH 00002DH Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Analog input enable register Port 6 direction register Vacancy System reserved area PWM operation mode control register Vacancy PWM reload register Serial mode register Serial control register Serial input data register/ Serial output data register Serial status register Interrupt enable register Interrupt source register Request level setting register A/D control status register
(Continued)
21
MB90660A Series
(Continued) Address
00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH
Register A/D data register Control status register 16-bit timer register/ 16-bit reload register Control status register 16-bit timer register/ 16-bit reload register Control status register 16-bit timer register/ 16-bit reload register Control status register 16-bit timer register/ 16-bit reload register Timer control status register Compare interrupt control register Timer mode control register Compare/data select register Compare buffer mode control register Zero detect output control register Output control buffer register Zero detect interrupt control register Output compare buffer register 0 Output compare buffer register 1 Output compare buffer register 2
Name ADCR TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1 TMCSR2 TMR2/ TMRLR2 TMCSR3 TMR3/ TMRLR3 TCSR CICR TMCR COER CMCR ZOCTR OCTBR ZICR OCPBR0 OCPBR1 OCPBR2
Access*2 R/W! R/W
Resource name A/D converter
Initial value XXXXXXXX 0 0 0 0 0 0XX 00000000 ----0000 XXXXXXXX XXXXXXXX 00000000 ----0000 XXXXXXXX XXXXXXXX 00000000 ----0000 XXXXXXXX XXXXXXXX 00000000 ----0000 XXXXXXXX XXXXXXXX 10000000 00000000 001-0000 ----0000 ----0000 ---X0000
16-bit reload timer 0 R/W R/W 16-bit reload timer 1 R/W R/W 16-bit reload timer 2 R/W R/W 16-bit reload timer 3 R/W R/W! R/W R/W! R/W R/W W R/W R/W! W W W Multi-function timer
11111111 0 - - - XXXX XXXXXXXX - - XXXXXX XXXXXXXX - - XXXXXX XXXXXXXX - - XXXXXX
(Continued)
22
MB90660A Series
(Continued) Address
00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H to 5EH 00005FH
Register Output compare buffer register 3 Compare clear buffer register Dead time control register Dead time setting register Dead time compare register Vacancy Timer pin control register Vacancy Machine clock division control register
Name OCPBR3 CLRBR DTCR DTSR DTCMR -- TPCR -- CDCR -- -- DIRR LPMCR CKSCR -- WDTC TBTC -- ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07
Access*2 W W R/W! W W *1 R/W *1 W *1 *1 R/W R/W! R/W! *1 R/W! R/W! *1 R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W!
Resource name
Initial value XXXXXXXX - - XXXXXX 00000000
Multi-function timer
--000000 00000000 XXX 0 XXXX XXXXXXXX
-- 16-bit reload timer -- UART -- -- Delayed interrupt generator module Low power -- Watchdog timer Timebased timer --
-- -001-000 -011-010 -- ----1111 -- -- -------0 00011000 11111100 -- X -XXX1 1 1 1--00100 -- 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111
000060H to Vacancy 8FH 000090H to System reserved area 9EH 00009FH 0000A0H 0000A1H Delayed interrupt source generate/ cancel register Low power mode control register Clock select register
0000A2H to System reserved area A7H 0000A8H 0000A9H 0000AAH to AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H Watchdog timer control register Timebase timer control register System reserved area Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07
Interrupt controller
(Continued)
23
MB90660A Series
(Continued) Address
0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to FFH
Register Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 System reserved area
Name ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 --
Access*2 R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! *1
Resource name
Initial value 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111
Interrupt controller
--
--
*1: Access prohibited *2: Registers marked "R/W!" in the access column include some bits that can only be read or only be written. For details, see the register list for each resource. * : When a register marked "R/W!", "R/W*" or "W" in the access column is accessed by a read-modify-write instruction (such as a bit set instruction), the bit operated on by the instruction will be set to the specified value, but a malfunction will occur if there are any other bits which can only be written. Therefore, do not access these locations using these instructions. Description of Initial Values 0: The initial value of this bit is "0". 1: The initial value of this bit is "1". *: The initial value of this bit is "1" or "0". (This is determined depending on the level of the MD0 to MD2 pins.) X: The initial value of this bit is undefined. -: This bit is not used. The initial value is undefined. Note: The initial value results for bits which can only be written when initialized by a reset. Note that this is not the value when read. Also, sometimes LPMCR, CKSCR and WDTC are initialized and sometimes they are not depending on the type of reset. If they are initialized, the initial value is used.
24
MB90660A Series
s INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT9 instruction Exception Multi-function timer DTTI input External interrupt #0 External interrupt #4 Multi-function timer trigger input or zero detect Multi-function timer zero detect Multi-function timer overflow, compare clear or zero detect External interrupt #1 Multi-function timer compare match External interrupt #5 PWM underflow External interrupt #2 External interrupt #6 16-bit reload timer #0 16-bit reload timer #1 16-bit reload timer #2 16-bit reload timer #3 End of A/D converter conversion Timebase timer interval interrupt UART send complete UART receive complete External interrupt #3 External interrupt #7 Delayed interrupt generator module x x x x
support
I2OS x x x x
Interrupt vector Number #08 #09 #10 #12 #13 #14 #15 #17 #19 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #34 #35 #37 #39 #40 #42 08H 09H 0AH 0CH 0DH 0EH 0FH 11H 13H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 22H 23H 25H 27H 28H 2AH Address FFFFDCH FFFFD8H FFFFD4H FFFFCCH FFFFC8H
Interrupt control register ICR -- -- -- ICR00 ICR01 Address -- -- -- 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H
FFFFC4H FFFFC0H FFFFB8H FFFFB0H FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H ICR07 FFFF94H FFFF90H ICR08 FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H FFFF74H FFFF70H FFFF68H FFFF60H ICR14 FFFF5CH FFFF54H ICR15 0000BFH 0000BEH ICR10 ICR11 ICR12 ICR13 0000BAH 0000BBH 0000BCH 0000BDH 0000B9H 0000B8H 0000B7H ICR06 0000B6H ICR02 ICR03 ICR04 ICR05
: indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (no stop request). : indicates that the interrupt request flag is cleared by the I2OS interrupt clear signal (with stop request). : indicates that the interrupt request flag is not cleared by the I2OS interrupt clear signal. Note: Do not specify I2OS activation in interrupt control registers that do not support I2OS.
25
MB90660A Series
s PERIPHERAL RESOURCES
1. Parallel Port
The MB90660A includes 39 I/O pins, 4 input pins, and 8 open-drain output pins. Port 0, 1, 2, 3 and 6 are I/O ports. They are used for input when the corresponding direction register value is "0", and for output when the value is "1". Port 5 is an open-drain port. It is used as a port when the analog input enable register is "0". Ports 40 to 43 are I/O ports. They are used for input when the corresponding direction register value is "0", and for output when the value is "1". Ports 44 to 47 are input ports which can only be used for reading data. (1) Register Configuration
bit Port Data Register Address : PDR1 000001H : PDR3 000003H Read/Write Initial value bit Port Data Register Address : PDR0 000000H : PDR2 000002H : PDR6 000006H (PDBR) Read/Write Initial value Port Data Register Address : 000005H Read/Write Initial value bit bit
15
14
13
12
11
10
9
8 PDR1, 3
PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0
PDx7 PDx6 PDx5 PDx4 PDx3 PDx2 PDx1 PDx0
PDR0, 2, 6
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 15 14 13 12 11 10 9 8 PDR5
PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) 7 6 5 4 3 2 1 0
Port Data Register Address : 000004H
PD47 PD46 PD45 PD44 PD43 PD42 PD41 PD40 (R) (X) (R) (X) (R) (X) (R) (X) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X)
PDR4
Read/Write Initial value
Notes: There are no register bits for bits 15 to 12 of Port 3. There is no register bit for bit 7 of Port 6. Bits 7 to 4 of Port 4 can only be used to read data.
26
MB90660A Series
Port Direction Register bit Address : DDR1 000011H : DDR3 000013H Read/Write Initial value bit Port Direction Register Address : DDR0 000010H : DDR2 000012H : DDR4 000014H : DDR6 000016H Read/Write Initial value
15
14
13
12
11
10
9
8 DDR1, 3
DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0
DDx7 DDx6 DDx5 DDx4 DDx3 DDx2 DDx1 DDx0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
DDR0, 2, 4, 6
Notes: There are no register bits for bits 15 to 12 of Port 3. There are not register bits for bits 7 to 4 of Port 4 There is no DDR for Port 5. There is no register bit for bit 7 of Port 6.
Analog Input Enable Register Address : 000015H Read/Write Initial value
bit
15
14
13
12
11
10
9
8 ADER
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1)
27
MB90660A Series
(2) Block Diagrams * I/O Ports
Data register read Internal data bus Data register Data register write Direction register Direction register write Pin
Direction register read
* Open-drain Ports (Also Used for Analog Input)
RMW (Read-modifywrite instruction) Internal data bus Data register read Data register Data register write ADER ADER register write
Pin
ADER register read
* Input Ports
Internal data bus
Pin Data register read
28
MB90660A Series
2. Multi-function Timer
The multi-function timer controls up to 7 realtime output pins, and includes the following functions. * Interval timer function It can output pulses or generate an interrupt at a fixed interval. * PWM output function Can perform output for a fixed cycle pulse while changing the duty ratio (ratio between "L" output width and "H" output width) in realtime. * 3-phase AC sine wave output (inverter control output) function Can perform 3-phase AC sine wave output using AC motor inverter control, etc. (using any setting for the nonoverlap interval) This timer also has the following characteristics. * Pulse cycle control using 14-bit timer A machine cycle of 1, 2, 8 or 16 can be selected based on pre-scalars as the clock source (Minimum resolution of 62.5 ns at 16 MHz operation). Can use a carrier frequency up to 30 KHz at 8-bit stop when used for AC motor control. Up count only or up/down count can be selected using the count mode selection. Possessing a buffer, cycle can be changed in realtime by transferring data from buffer upon zero detect. * Duty control using compare registers Possessing four compare registers, output pulse duty can be set for four separate channels. Each possessing a separate buffer, duty can be changed in realtime by transferring data from buffer upon zero detect or comparison. * Non-overlap control using dead time timer Dead time timer can be used to generate PWM output for three channels or even reversed signals with nonoverlap, thus allowing an AC motor control wave (U, V, W, X, Y, Z) to be generated. A machine cycle of 1, 4, 8 or 32 can be selected based on pre-scalars as the clock source for the dead timer (Minimum resolution of 62.5 ns at 16 MHz operation) * Forced stop control using DTTI pin input The forced pin output level can be fixed by DTTI pin input or software. Inactive control can be performed during AC motor control using DTTI pin input. External pin control even during vibration stop can be performed through clockless DTTI pin input. * Event detection and interrupt generation using various flags Flags can be set and/or interrupts generated upon zero detect, overflow, detect of match with compare registers, or clear by TRG pin input, or any match of the compare registers for the four channels for the 14-bit timer (also possible to disable interrupt output).
29
MB90660A Series
(1) Register Configuration
Address : Address : Address : Address : Address :
000040H 000041H 000042H 000043H 000044H
8 bits TCSR CICR TMCR COER CMCR ZOCTR OCTR
(R/W) (R/W) (R/W) (R/W) (R/W) (W)
Timer control status register Compare interrupt control register Timer mode control register Compare/data select register Compare buffer mode control register Zero detect output control register Output control register
Address : 000045H
Address : 000046H Address : 000047H
OCTBR ZICR 14 bits OCPR0 to 3
(R/W) Output control buffer register (R/W) Zero detect interrupt control register Output compare registers 0 to 3
Address : 000048H to : 00004FH
OCPBR0 to 3 14 bits CLRR
(W)
Output compare buffer registers 0 to 3
(W) (W)
Compare clear register Compare clear buffer register
Address : 000050H : 000051H Address : 000052H Address : 000053H Address : 000054H Address : 000006H
CLRBR DTCR DTSR DTCMR PDBR
(R/W) Dead time timer control register Dead time setting register (W) Dead time compare register (W) (W) Port data buffer register
30
MB90660A Series
(2) Block Diagrams * Timer/wave generator block diagram
CLRR, CLRBR Reverse or Clear Interrupt Control IIOS TCIE, TCIR TZIE, TZIR TMIE, TMIR CIE3 to 0, CIR3 to 0 Timer Clear Zero detect interrupt Zero detect Zero detect interrupt mask ZOSC, IME, CYC3 to 0 Timer interrupt Compare interrupt
Comparator
TRG (External Input)
14-bit Timer STCR, TMST, MODE CES1, 0 TCS1, 0
Count Clock
Pre-scalar (1, 2, 8 or 16 machine cycles)
14
Zero detect
Zero detect pin control ZSB0
Set, Reset
Comparator, pin control RO01, 0
Set, Reset, Transfer
PDR6 PD66
RT0 (External Output)
OCPR0, OCPBR0
Zero detect pin control ZSB1
Set, Reset
Comparator, pin control RO11, 0
Set, Reset, Transfer
PDR6 PD60
RT1 (to Output Selector)
OCPR1, OCPBR1
Zero detect pin control ZSB2
Set, Reset
Comparator, pin control RO21, 0
Set, Reset, Transfer
PDR6 PD61
RT2 (to Output Selector)
OCPR2, OCPBR2
Zero detect pin control ZSB3
Set, Reset
Transfer request
Set, Reset, Comparator, pin control Transfer RO31, 0
PDR6 PD62
RT3 (to Output Selector)
Buffer transfer control TREN, TMSK, BFS1, 0
OCPR3, OCPBR3
31
MB90660A Series
* Output selector/dead time generator block diagram
DTTI interrupt DTIE, DTIF Flag set DTTI control DTTI (External input) TOCE, TOC1, 0 NRSL
DTTI Interrupt
Inactive
RT1 (from wave generator) Comparator
P60/RT1/U Compare Dead time wave generator U X Selector P63/X (External output)
8-bit timer Count clock Pre-scalar Division select Inactive Active level Mode select
RT2 (from wave generator) Comparator
P61/RT2/V Compare Dead time wave generator V Y Selector P64/Y (External output)
8-bit timer Count clock Pre-scalar Division select Inactive Active level Mode select
RT3 (from wave generator) Comparator
P62/RT3/W Compare Dead time wave generator W Z Selector P65/Z (External output)
8-bit timer Count clock Pre-scalar Division select Wave control 8 DTCMR DMOD, DT1, 0 DCS1, 0 Active level Mode select
32
MB90660A Series
3. UART
The UART is a serial I/O port for asynchronous (start/stop) or CLK synchronous communications with external resources. It has the following characteristics: * * * * Full duplex double buffering Asynchronous (start/stop) or CLK synchronous communications Multiprocessor mode support Internal dedicated baud-rate generator Asynchronous : 19230/9615/31250/4808/2404/1202 bps CLK synchronous * * * * : 2 M/1 M/500 K/250 K bps Free baud-rate setting based on external clock Error detection functions (parity, framing and overrun) Use of NRZ coded transfer signal Supports intelligent I/O services
(1) Register Configuration
15 SCR SSR CDCR 8 bits
87 SMR SIDR (R)/SODR (W)
0 (R/W) (R/W) (W) 8 bits
bit Address : 000024H bit Address : 000025H bit Address : 000026H bit Address : 000027H bit Address : 00005FH
7 MD1 15 PEN 7 D7 15 PE 15 -
6 MD0 14 P 6 D6 14 ORE 14 -
5 CS2 13 SBL 5 D5 13
4 CS1 12 CL 4 D4 12
3 CS0 11 A/D 3 D3 11
2 - 10 REC 2 D2 10 - 10
1
0 Serial mode register (SMR)
SCKE SOE 9 RXE 1 D1 9 RIE 9 8 TXE 0 D0 8 TIE 8
Serial control register (SCR) Serial input register Serial output register (SIDR/SODR) Serial status register (SSR)
FRE RDRF TDRE 13 - 12 - 11
DIV3 DIV2 DIV1 DIV0
Machine clock division control register (CDCR)
33
MB90660A Series
(2) Block Diagram
Control signal
Receive interrupt (to CPU) SCK Transfer clock Clock selector Receive clock Send interrupt (to CPU)
Dedicated baud rate generator 16-bit timer0 (connected internally) External clock Receive controller Start bit detect circuit Receive bit counter Receive parity counter
Send controller
SIN
Send start circuit
Send bit counter
Send parity counter
SOT
Receive status determination circuit
Receive shifter
Send shifter
Receive end SIDR Receive error generator signal for EI2OS (to CPU) F2MC-16 bus
Send start SODR
SMR register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR register
PEN P SBL CL A/D REC RXE TXE
SSR register
PE ORE FRE RDRF TDRE RIE TIE
Control signal
34
MB90660A Series
4. 10-bit, 8-channel A/D Converter (with 8-bit Resolution Mode)
This 10-bit, 8-channel A/D converter is used to convert analog input voltage to corresponding digital values. It has the following features. * Conversion time: 6.13 s per channel (includes sample and hold time at 98 machine cycles/machine clock of 16 MHz) * Sample hold time: 3.75 s per channel (60 machine cycles per machine clock of 16 MHz) * RC-type sequential approximation conversion with sample and hold circuits * 10-bit or 8-bit resolution * Analog input can be selected from 8 channels Single conversion mode : One channel selected for conversion Scan conversion mode : Consecutive multiple channels converted (programmable with max. eight channels) : Once one channel is converted, operations stop and the device waits until started again (conversion start can be synchronized)
Repetitive conversion mode : Data on the specified channel is converted repeatedly Stop conversion mode
* At the end of each A/D conversion, an interrupt request to the CPU can be generated. This interrupt can be used to activate I2OS or transfer A/D conversion results to memory, making it useful when continuous processing is desired. * Conversion can be triggered by software, an external trigger (falling edge), and/or a timer (rising edge). (1) Register Configuration
bit 15 14 A/DControl status register (upper) BUSY INT Address : 00002DH Read/Write Initial value bit A/D Control status register (lower) Address : 00002CH Read/Write Initial value A/D Data register (upper) Address : 00002FH Read/Write Initial value A/D Data register (lower) Address : 00002EH Read/Write Initial value bit bit
13
12
11
10
9
8
Reserved
INTE PAUS STS1 STS0 STRT (W) (0) 1
ADCS
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) 7 MD1 6 5 4 3 2
(-) (0) 0 ADCS
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 S10 (R/W) (0) 7 D7 (R) (X) 14 - (R) (0) 6 D6 (R) (X) 13 - (R) (0) 5 D5 (R) (X) 12 - (R) (0) 4 D4 (R) (X) 11 - (R) (0) 3 D3 (R) (X) 10 - (R) (0) 2 D2 (R) (X) 9 D9 (R) (X) 1 D1 (R) (X) 8 D8 (R) (X) 0 D0 (R) (X) ADCR ADCR
35
MB90660A Series
(2) Block Diagram
AVCC AVR AVSS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Input circuit
Sequential comparison register
Comparator Data bus Decoder Data register ADCR0, 1 A/D control register 1 A/D control register 2 ADCS0, 1 Trigger start Operation clock Pre-scalar
Sample and hold circuits
ATG
Multi-function timer (RT0 output)
Timer start
Peripheral clock
36
MB90660A Series
5. PWM Timer
This block, which is an 8-bit reload timer module, outputs the pulse width modulation (PWM) using pulse output control corresponding to the timer operation. In terms of hardware, this block possesses an 8-bit down counter, two 8-bit reload registers for setting "L" width and "H" width, a control register, external pulse output pin, and interrupt output circuit to achieve the following functions. * PWM output operation : Pulse waves of any period and duty factor are output. This block can also be used as a D/A converter with an external circuit. Interrupt requests can be output based on counter underflow.
(1) Register Configuration
PWM operation mode control register Address: 000020H PWM reload register 000022H 000023H
(2) Block Diagram
8 bits PWMC (R/W) PRLL PRLH (R/W) (R/W)
(Functions) Operation mode control Hold "L" pulse width reload value Hold "H" pulse width reload value
PWM Output enabled TBT output main clock divided by 4 TBT output main clock divided by 512 (Port) TBT: Timebase timer
PWMO Output latch Clear PEN
Reverse
PCNT (down counter) Count clock selection Reload L/H select L/H selector
IRQ
PRLL
PRLBH PWMC Operation mode control
PRLH
F2MC-16 bus
37
MB90660A Series
6. 16-bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, control register, and 4 timer pins (I/O set by timer pin select register). Three internal clocks and an external clock can be selected as input clocks. A toggle output waveform is output at the output pin (TOT) in reload mode, while a square wave indicating that the timer is counting is output at the output pin in single-shot mode. The input pin (TIN) can be used for event input in even count mode, and for trigger input or gate input in internal clock mode. This product has this timer built into four channels. (1) Register Configuration
Control status register (upper) bit Address : channel 0 000031H : channel 1 000035H : channels 2 000039H : channels 3 00003DH Read/Write Initial value
15 - (-) (-) - (-) (-)
14 - (-) (-)
13 - (-) (-)
12
11
10
9
8
CSL1 CSL0 MOD2 MOD1 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0)
Control status register (lower) bit 7 6 5 4 3 2 1 0 Address : channel 0 000030H : channel 1 000034H MOD0 Reserved OUTL RELD INTE UF CNTE TRG : channels 2 000038H : channels 3 00003CH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/Write (0) (0) (0) (0) (0) (0) (0) (0) Initial value 16-bit timer register (upper) 16-bit reload register (upper) Address : channel 0 000033H : channel 1 000037H : channels 2 00003BH : channels 3 00003FH Read/Write Initial value 16-bit timer register (lower) 16-bit reload register (lower) Address : channel 0 000032H : channel 1 000036H : channels 2 00003AH : channels 3 00003EH Read/Write Initial value Timer pin control register (upper) Address : 000057H Read/Write Initial value Timer pin control register (lower) Address : 000056H Read/Write Initial value bit bit 15 14 13 12 11 10 9 8
TMCSR 0 to 3
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 7 6 5 4 3 2 1 0 TMR/ TMRLR 0 to 3 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 15 - (-) (-) 7 - (-) (-) 14 13 12 11 - (-) (-) 3 - (-) (-) 10 9 8
OTE3 CSB3 CSA3 (R/W) (R/W) (R/W) (0) (1) (1) 6 5 4
OTE2 CSB2 CSA2 (R/W) (R/W) (R/W) (0) (1) (0) 2 1 0 TPCR
OTE1 CSB1 CSA1 (R/W) (R/W) (R/W) (0) (0) (1)
OTE0 CSB0 CSA0 (R/W) (R/W) (R/W) (0) (0) (0)
38
MB90660A Series
(2) Block Diagram
16 16-bit reload register
8
Reload RELD 16-bit down counter UF OUTL GATE CSL1 Clock selector CSL0 Trigger TRG CNTE Clear I2OSCLR OUT CTL INTE UF IRQ
16 2 F2MC-16 bus
2 IN CTL EXCK --- 21 23 25 Prescaler clear 3 MOD2 MOD1 Peripheral clock MOD0 Serial baud rate (channel 0 only) TIN TOT
3
I/O pins for timer* 16-bit reload timer Channel 0 16-bit reload timer Channel 1 16-bit reload timer Channel 2 16-bit reload timer Channel 3 TIN0 TOT0 TIN1 TOT1 TIN2 TOT2 TIN3 TOT3 TIM0
Selector
TIM1
TIM2
TIM3
* : Timer channel and direction (I/O) can be selected for each pin.
39
MB90660A Series
7. External Interrupts
In addition to "H" and "L", rising and falling edge can be selected as the external interrupt level for a total of four interrupt level types. (1) Register Configuration
Interrupt enable register Address : 000028H Read/Write Initial value Interrupt source register Address : 000029H Read/Write Initial value
bit
7 EN7
6 EN6
5 EN5
4 EN4
3 EN3
2 EN2
1 EN1
0 EN0 ENIR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) bit 15 ER7 14 ER6 13 ER5 12 ER4 11 ER3 10 ER2 9 ER1 8 ER0 EIRR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 LB7 14 LA7 13 LB6 12 LA6 11 LB5 10 LA5 9 LB4 8 LA4
bit Request level setting register (upper) Address : 00002BH Read/Write Initial value bit Request level setting register (lower) Address : 00002AH Read/Write Initial value
(2) Block Diagram
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 LB3 6 LA3 5 LB2 4 LA2 3 LB1 2 LA1 1 LB0 0 LA0 ELVR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0)
8
Interrupt enable register
Gate
8
IRQ
F2MC-16 bus
Source F/F
Edge detector
8
Request input
8
Interrupt source register
16
Request level setting register
40
MB90660A Series
8. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate an interrupt for task switching. If this module is used, an interrupt request to the F2MC-16L CPU can be generated or cancelled by software. (1) Register Configuration
Delayed interrupt request generation/cancel register Address : 000009H Read/Write Initial value
bit
15 - (-) (-)
14 - (-) (-)
13 - (-) (-)
12 - (-) (-)
11 - (-) (-)
10 - (-) (-)
9 - (-) (-)
8 R0 (R/W) (0) DIRR
The DIRR register controls the generation and cancellation of delayed interrupt requests. A delayed interrupt request is generated when "1" is written to this register, while a delayed interrupt request is cancelled when "0" is written here. Request cancel status results upon reset. Although either "0" or "1" may be written into reserved bits, we recommend using the set bit and clear bit instructions when accessing this register in consideration of possible future extensions. (2) Block Diagram
F2MC-16 bus
Delayed interrupt source generation/ cancel decoder
Source latch
41
MB90660A Series
9. Watchdog Timer and Timebase Timer Functions
The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit timebase timer as the clock source, a control register, and a watchdog reset controller. In addition to an 18-bit timer, the timebase timer consists of a circuit for controlling interval interrupts. Note that the timebase timer uses the main clock regardless of the status of the MCS bit within the CKSCR register. (1) Register Configuration
bit Watchdog timer control register Address : 0000A8H Read/Write Initial value bit Timebase timer control register Address : 0000A9H Read/Write Initial value
(2) Block Diagram
7 PONR (R) (X) 15
Reserved
6 - (-) (-) 14 - (-) (-)
5
4
3
2
1
0 WT0 (W) (1) 8 TBTC WDTC
WRST ERST SRST WTE WT1 (R) (X) 13 - (-) (-) (R) (X) 12 (R) (X) 11 (W) (1) 10 (W) (1) 9
TBIE TBOF TBR TBC1 TBC0 (R/W) (R/W) (0) (0) (W) (1) (R/W) (R/W) (0) (0)
(-) (1)
TBTC TBC1 Selector TBC0 TBR TBIE AND TBOF F2MC-16 bus S QR 212 214 216 219 TBTRES Clock input 22 Timebase timer 29 212 214 216 219
Main clock (OSC oscillation)
to PWM timer
Timebase interrupt WDTC WT1 Selector WT0 WTE 2-bit counter OF CLR Watchdog reset generator CLR to WDGRST internal reset generator
PONR WRST ERST SRST
from power-on generator
RST pin from RST bit of STBYC register
42
MB90660A Series
10. Low Power Consumption Controller (CPU intermittent operation function, stable oscillation wait time, and clock multiplier function)
The following operation modes are available: PLL clock mode, PLL sleep mode, clock mode, main clock mode, main sleep mode and stop mode. Operation modes other than PLL clock mode are classified as low power consumption modes. Main clock mode and main sleep mode are modes where the microcontroller operates using the main clock (OSC oscillation clock) only. In these modes, the main clock divided by two is used as the operation clock and the PLL clock (VCO oscillation clock) is stopped. In PLL sleep mode and main sleep mode, only the operation clock of the CPU is stopped, while operations besides the CPU clock continue. In clock mode, only the timebase timer is allowed to operate. In stop mode, oscillation is stopped, allowing data to be held at the lowest power consumption possible. The CPU intermittent operation function causes the clock provided to the CPU to function intermittently when accessing registers, internal memory, internal resources and the external bus. This allows processing to be performed at lower power consumption by reducing the CPU execution speed while continuing to provide a high speed clock to internal resources. The PLL clock multiplier can be selected as 1, 2, 3 or 4 using the CS1 and CS0 bits. The stable oscillation wait time for the main clock when stop mode is cancelled can be set using the WS1 and WS0 bits. (1) Register Configuration
Low power consumption mode bit control register Address : 0000A0H Read/Write Initial value Clock selection register Address : 0000A1H Read/Write Initial value bit
7 STP (W) (0) 15
Reserved
6 SLP (W) (0) 14
5 SPL (R/W) (0) 13
4 RST (W) (1) 12
3
Reserved
2 CG1
1 CG0
0
Reserved
LPMCR
(-) (1) 11
Reserved
(R/W) (R/W) (0) (0) 10 MCS 9 CS1
(-) (0) 8 CS0 CKSCR
MCM WS1 WS0 (R) (1) (R/W) (R/W) (1) (1)
(-) (1)
(-) (1)
(R/W) (R/W) (R/W) (1) (0) (0)
43
MB90660A Series
(2) Block Diagram
CKSCR MCM MCS CKSCR CS1 CS0 CPU Clock selector 0, 9, 17 or 33 intermittent cycle select PLL multiplier circuit 1 2 3 4 1 2 Clock generator for CPU CPU clock Main clock (OSC oscillation)
LPMCR CG1 CG0 CPU intermittent operation function Cycle count selector Peripheral resource clock
F2MC-16 bus
LPMCR SLP STP Standby controller RST cancel
Clock generator for peripheral resources
Interrupt request or RST CKSCR WS1 WS0 LPMCR SPL Pin high-impedance controller Stable oscillation wait time selector 24 213 215 218 Clock input Timebase timer 22 to PWM timer 29
212 214 216 219 Pin HI-Z
LPMCR Internal reset generator RST
RST pin Internal RST
to watchdog timer
WDGRST
44
MB90660A Series
11. Interrupt Controller
The interrupt control register is located within the interrupt controller. Its status conforms to all I/O possessed by the interrupt function. This register includes the following three functions. * Sets the interrupt level of the corresponding peripheral resource * Selects whether to use conventional interrupts or extended intelligent I/O services for the interrupt of the corresponding peripheral resource * Selects the channel for the extended intelligent I/O services (1) Register Configuration
Interrupt control register bit 15 14 13 12 11 10 9 8 Address : ICR01 0000B1H : ICR03 0000B3H : ICR05 0000B5H ICS1 ICS0 : ICR07 0000B7H ICS3 ICS2 or ISE IL2 IL1 IL0 or : ICR09 0000B9H S1 S0 : ICR11 0000BBH : ICR13 0000BDH : ICR15 0000BFH Read/Write Initial value (W) (0) (W) (0) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (1) (1) (1)
ICR01, 03, 05, 07, 09, 11, 13, 15
Interrupt control register bit 7 6 5 4 3 2 1 0 Address : ICR00 0000B0H : ICR02 0000B2H : ICR04 0000B4H ICS1 ICS0 : ICR06 0000B6H ICS3 ICS2 or ISE IL2 IL1 IL0 or : ICR08 0000B8H S1 S0 : ICR10 0000BAH : ICR12 0000BCH : ICR14 0000BEH (W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/Write (0) (0) (0) (0) (0) (1) (1) (1) Initial value
ICR00, 02, 04, 06, 08, 10, 12, 14
Note: Since read-modify-write type instructions can cause a malfunction, do not access using these instructions.
45
MB90660A Series
(2) Block Diagram
4
ISE
IL2
IL1
IL0
4
Determines interrupt/I2OS priority level
32
Interrupt request/ I2OS request (peripheral resource)
I2OS select 4 ICS3 ICS2 ICS1 ICS0 4
4 Selects I2OS vector
3 4
(CPU) Interrupt level I2OS vector (CPU)
F2MC-16 bus
2
S1
S0
2
Detects I2OS end condition
2
I2OS end condition
46
MB90660A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter Symbol VCC Power supply voltage Programming voltage Input voltage*2 Output voltage*2 "L" level maximum current*3 "L" level average output current*4 "L" level total average output current*5 "H" level maximum output current*3 "H" level average output current*4 "H" level total average output current*5 Power consumption Operating temperature Storage temperature *1: *2: *3: *4: *5: *6: *7: *8: AVCC* VAVR* VPP VI VO IOL1 IOL2 IOLAV1 IOLAV2 IOLAV1 IOLAV2 IOH IOHAV IOHAV Pd TA Tstg
1 1
(VSS = AVSS = 0.0 V)
Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -- -- -- -40 -55 Max. VSS + 7.0 VSS + 7.0 VSS + 7.0 13.0 VCC + 0.3 VCC + 0.3 10 30 4 20 30 60 -10 -4 -40 400 +85 +150
Unit V V V V V V mA mA mA mA mA mA mA mA mA mW C C *7 *8 *7 *8 *7 *8 *6
Remarks
AVCC and VAVR must not exceed VCC. VI and VO must not exceed VCC + 0.3 V. Maximum output current specifies the peak value of one corresponding pin. Average output current specifies the average current within a 100 ms interval flowing through one corresponding pin. Average total output current specifies the average current within a 100 ms interval flowing through all corresponding pins. MD2 pin of MB90P663A Pins excluding P60/RT1/U, P61/RT2/V, P62/RT3/W, P63/X, P64/Y and P65/Z pins P60/RT1/U, P61/RT2/V, P62/RT3/W, P63/X, P64/Y and P65/Z pins
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
47
MB90660A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter Power supply voltage Operating temperature
Symbol VCC VCC TA
Ratings Min. 2.7 2.0 -40 Max. 5.5 5.5 +85
Unit V C
Remarks During normal operation Stop operation status is held
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
48
MB90660A Series
3. DC Characteristics
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name
Conditions VCC = 4.5 V IOH = -4.0 mA VCC = 2.7 V IOH = -1.6 mA VCC = 4.5 V IOL = 4.0 mA VCC = 2.7 V IOL = 2.0 mA VCC = 4.5 V IOL = 15.0 mA VCC = 2.7 V IOL = 2.0 mA -- -- -- -- -- -- VCC = 5.5 V VSS < VI < VCC
When VCC = 5.0 V When VCC = 3.0 V When VCC = 5.0 V When VCC = 3.0 V Internal 16 MHz operation Internal 16 MHz operation Internal 8 MHz operation Internal 8 MHz operation
Value Min.
VCC - 0.5 VCC - 0.3
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 160 50 25 10 5 0.1 10 0.1
Max. -- -- 0.4 0.4 1.0 0.4
VCC + 0.3 VCC + 0.3 VCC + 0.3
Unit V V V V V V V V V V V V A k k k k mA * *
Remarks
"H" level output voltage
VOH
Except P50 to P57
-- -- -- -- 0.7 VCC 0.8 VCC
VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3
VOL1 "L" level output voltage VOL2
Except P60 to P65
P60 to P65 Pins except VIHS, VIHM
Hysteresis input pins
VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage Input leakage current Pull-up resistor Pull-down resister VILS VILM IIL RPUP
MD pin Pins except VILS, VILM
Hysteresis input pins
0.3 VCC 0.2 VCC
VSS + 0.3
MD pin
Except P50 to P57
-10 25 40 25 40 -- -- -- -- -- -- --
10 100 200 200 400 70 30 20 10 10 -- 10
Pins for which pull-up option is selected Pins for which pull-down options selected When VCC = 5.0 V
RPDN ICC ICCS
During normal operation
mA During sleep mA During normal operation
Supply current
ICC When VCC = 3.0 V ICCS ICCH -- Except AVCC, AVSS, VCC and VSS P50 to P57
mA During sleep A pF A N channel Tr off During stop
TA = 25C -- --
Input capacitance
Open-drain output leakage current
CIN Ileak
* : Applies to pins P40 to P47, P50 to P57, P60 to P66, DTTI and RST.
49
MB90660A Series
4. AC Characteristics
(1) Clock Timing Values * Used at VCC = 5.0 V 10%
(VCC = +4.5 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Oscillation frequency Oscillation cycle time Frequency fluctuation ratio* (when locked) Input clock pulse width Input clock rising and falling times Internal operating clock frequency Internal operating clock cycle time
Symbol
Pin name X0, X1 X0, X1 -- X0 X0 -- --
Conditions -- -- -- -- -- -- --
Value Min. 3 31.25 -- 10 -- 1.5 62.5 Max. 32 333 3 -- 5 16 666
Unit MHz ns % ns ns MHz ns
Remarks
FC tC yf PWH PWL tcr tcf fCP tCP
Use duty ratio of 30% to 70% as guideline
* : The frequency fluctuation ratio represents the maximum fluctuation from the central frequency as a percentage when a multiplier is locked.
+ f0 + x 100 (%) Central frequency f0 - -
f=
* Used at VCC = 2.7 V (minimum)
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Oscillation frequency Oscillation cycle time Input clock pulse width Input clock rising and falling times Internal operating clock frequency Internal operating clock cycle time 50
Symbol
Pin name X0, X1 X0, X1 X0 X0 -- --
Conditions -- -- -- -- -- --
Value Min. 3 62.5 20 -- 1.5 125 Max. 16 333 -- 5 8 666
Unit MHz ns ns ns MHz ns
Remarks
FC tC PWH PWL tcr tcf fCP tCP
Use duty ratio of 30% to 70% as guideline
MB90660A Series
(2) Recommended Resonator Manufacturers * Sample Application of Piezoelectric Resonator (FAR Family)
X0
X1 R
*1
FAR
*1
C1
*2
C2 *1: Fujitsu Acoustic Resonator
FAR part number (built-in capacitor type) FAR-C4CC-02000-L20 FAR-C4SA-04000-M01 FAR-C4CB-04000-M00 FAR-C4CB-08000-M02 FAR-C4CB-12000-M02 FAR-C4CB-16000-M02 FAR-C4CB-20000-L14B FAR-C4CB-24000-L14A Inquiry: FUJITSU LIMITED
Frequency (MHz) 2.00 4.00 8.00 12.00 16.00 19.80 23.76
Dumping resistor 510 -- -- -- -- -- -- --
Initial deviation of FAR frequency (TA = +25C) 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5%
Temperature characteristics of Loading*2 FAR frequency capacitors (TA = -20C to +60C) 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% 0.5% Built-in
51
MB90660A Series
* Sample Application of Ceramic Resonator
X0
X1 R *
C1
C2
* Mask Products Resonator manufacturer* Resonator KBR-2.0MS PBRC2.00A KBR-4.0MSA KBR-4.0MKS PBRC4.00A PBRC4.00B KBR-6.0MSA KBR-6.0MKS PBRC6.00A PBRC6.00B KBR-8.0M PBRC8.00A PBRC8.00B KBR-10.0M PBRC10.00B KBR-12.0M PBRC12.00B Frequency (MHz) 2.00 C1 (pF) 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in C2 (pF) 150 150 33 Built-in 33 Built-in 33 Built-in 33 Built-in 33 33 Built-in 33 Built-in 33 Built-in R -- -- 680 680 680 680 -- -- -- -- 560 -- -- 330 680 330 680 (Continued)
4.00
Kyocera Corporation
6.00
8.00 8.00 10.00 12.00
52
MB90660A Series
(Continued)
Resonator manufacturer* Resonator CSA2.00MG040 CST2.00MG040 CSA4.00MG040 CST4.00MGW040 CSA6.00MG CST6.00MGW CSA8.00MTZ CST8.00MTW CSA10.00MTZ CST10.00MTW CSA12.00MTZ CST12.00MTW CSA16.00MXZ040 CST16.00MXW0C3 CSA20.00MXZ040 CSA24.00MXZ040 CSA32.00MXZ040 Frequency (MHz) 2.00 4.00 6.00 8.00 10.00 12.00 16.00 20.00 24.00 32.00 C1 (pF) 100 Built-in 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 15 Built-in 10 5 5 C2 (pF) 100 Built-in 100 Built-in 30 Built-in 30 Built-in 30 Built-in 30 Built-in 15 Built-in 10 5 5 R -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Murata Mfg. Co., Ltd.
Inquiry: Kyocera Corporation * AVX Corporation North American Sales Headquarters: TEL 1-803-448-9411 * AVX Limited European Sales Headquarters: TEL 44-1252-770000 * AVX/Kyocera H.K. Ltd. Asian Sales Headquarters: TEL 852-363-3303 Murata Mfg. Co., Ltd. * Murata Electronics North America, Inc.: TEL 1-404-436-1300 * Murata Europe Management GmbH: TEL 49-911-66870 * Murata Electronics Singapore (Pte.) Ltd.: TEL 65-758-4233
53
MB90660A Series
* Clock Timing
tC 0.8 VCC 0.2 VCC PWH tcf PWL tcr
* PLL Operation Warranty Range
Relationship between clock frequency and supply voltage 5.5 4.5 3.3 2.7 0 1.5 3 8 16 Internal clock fCP (MHz) Normal operating range
Power supply VCC (V)
PLL operation warranty range
Relationship between oscillator frequency and internal operating clock frequency Multiplied Multiplied by 4 by 3 Multiplied by 2 Multiplied by 1 No multiplication
16 Internal clock fCP (MHz)
12 9 8
4 FC (MHz)
0
34
8
16 Oscillation clock
24
32
Note: Even in the case of evaluation tool, operation is assured down to 2.7 V.
AC specification values are specified for the measured reference voltages given below. * Input Signal Waveforms
Hysteresis input pin 0.8 VCC 0.2 VCC Pins except hysteresis input and MD input 0.7 VCC 0.3 VCC
* Output Signal Waveforms
Output pin 2.4 V 0.8 V
54
MB90660A Series
(3) Reset Input Specifications
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Reset input time
Symbol
Pin name RST
Conditions --
Value Min. 16 Max. --
Unit Machine cycle
Remarks
tRSTL
tRSTL
RST
0.2 VCC 0.2 VCC
(4) Power-On Reset
(VSS = 0.0 V, TA = -40C to +85C)
Parameter Power supply rise time Power supply cutoff time
Symbol
Pin name VCC VCC
Conditions
Value Min. -- Max. 30 --
Unit ms ms *
Remarks
tR tOFF
--
1
Due to repeated operations
* : VCC should be lower than 0.2 V before power supply rise. Notes: * The above specifications are the numeric values needed for causing a power-on reset. * There are built in resisters initialized only by power on reset in the device. Turn on power supply according to the specification at the point of this initialization.
tR 2.7 V
VCC
0.2 V
An abrupt change in the supply voltage may activate power-on reset. If the supply voltage must be changed during operation, the voltage change should be smooth without sudden fluctuations.
5.0 V
VCC
2.0 V RAM data maintained VSS A rise time of 50 mV/ms or less is recommended.
55
MB90660A Series
(5) UART timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock H pulse width Serial clock L pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Symbol
Pin name SCK SCK SOT SCK SIN SCK SIN SCK SCK SCK SOT SCK SIN SCK SIN
Conditions -- VCC = 5.0 V 10% VCC = 3.0 V 10% VCC = 5.0 V 10% VCC = 3.0 V 10% VCC = 5.0 V 10% VCC = 3.0 V 10% -- -- VCC = 5.0 V 10% VCC = 3.0 V 10% VCC = 5.0 V 10% VCC = 3.0 V 10% VCC = 5.0 V 10% VCC = 3.0 V 10%
Value Min. 8 tCP -80 -120 100 200 60 120 4 tCP 4 tCP -- -- 60 120 60 120 Max. -- 80 120 -- -- -- -- -- -- 150 200 -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
CL = 80 pF + 1 TTL for internal clock operation output pin
CL = 80 pF + 1 TTL for external clock operation output pin
Notes: * These are AC specification during CLK synchronous mode. * CL is the load capacity value assigned to the pin during testing. * tCP is the machine cycle time (unit: ns).
56
MB90660A Series
* Internal Shift Clock Mode
tSCYC
SCK
2.4 V 0.8 V
tSLOV
0.8 V
SOT
2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
* External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC 0.2 VCC
tSLOV
0.8 VCC
0.2 VCC
SOT
2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
57
MB90660A Series
(6) Timer input timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter Input pulse width
Symbol
Pin name TIM0 to TIM3
Conditions --
Value Min. 4 tCP Max. --
Unit ns
Remarks
tTIWH tTIWL
0.7 VCC
0.7 VCC 0.3 VCC 0.3 VCC
tTIWH
tTIWL
(7) Trigger input timing
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name ATG, DTTI, TRG, INT4 to INT7 ATG, DTTI, TRG, INT0 to INT3
Conditions
Value Min. 5 tCP Max. -- --
Unit ns ns
Remarks
Input pulse width
tTRGH tTRGL
-- 5 tCP
* INT4 to INT7
0.7 VCC
0.7 VCC 0.3 VCC 0.3 VCC
tTRGH
tTRGL
* INT0 to INT3
0.7 VCC
0.8 VCC 0.2 VCC 0.2 VCC
tTRGH
tTRGL
58
MB90660A Series
5. Electrical Characteristics of A/D Converter
(AVCC = VCC = +2.7 V to +5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVR, TA = -40C to +85C)
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog port input voltage Analog input voltage Reference voltage Supply current Reference voltage supply current Variation between channels
Symbol -- -- -- -- VOT VFST -- IAIN VAIN -- IA IAH IR IRH --
Pin name -- -- -- -- AN0 to AN7 AN0 to AN7 -- AN0 to AN7 AN0 to AN7 AVR AVCC AVCC AVR AVR AN0 to AN7
Value Min. -- -- -- -- -1.5 AVR - 4.5 6.125 -- 0 3.5 -- -- -- -- --
*1 *2
Typ. 10 -- -- -- +0.5 AVR - 1.5 -- -- 0.1 -- -- 3 -- 200 -- --
Max. 10 3.0 2.0 1.5 +2.5 AVR + 0.5 -- -- 10 AVR AVCC -- 5 5
*3
Unit bit LSB LSB LSB LSB LSB s s A V V mA A A A LSB
12.25
--
*3
4
*1: VCC = 5.0 V 10% at 16 MHz machine clock *2: VCC = 3.0 V 10% at 8 MHz machine clock *3: Current when CPU is stopped and A/D converter is not operating (when VCC = AVCC = AVR = 5.0 V) Notes: * The relative error becomes larger as the reference voltage (AVR) becomes smaller. * Be sure to use the A/D converter only when output impedance of the external analog input circuit meets the following conditions. External circuit output impedance < approx. 7 k * If the output impedance of the external circuit is too high, there may not be enough time to sample the analog voltage. (Sampling time = 3.75 s @4 MHz (equivalent to internal 16 MHz when multiplying by 4)) * For an external capacitor to be provided outside the chip, its capacity should desirably be thousands times larger than of the capacity in the chip taking in consideration the influence of the capacity destribution of the external and internal capacitors. * Figure Model of Analog Input Circuit
Sample and hold circuit Analog input RON1 RON2 RON3 RON4 C1 C0 Comparator
RON1 = Approx. 1.5 k (VCC = 5.0 V) RON2 = Approx. 0.5 k (VCC = 5.0 V) RON3 = Approx. 0.5 k (VCC = 5.0 V) RON4 = Approx. 0.5 k (VCC = 5.0 V) C0 = Approx. 60 pF C1 = Approx. 4 pF Note: Use the values shown here as guidelines.
59
MB90660A Series
6. Definitions of A/D Converter Terms
Resolution Total error Linearity error : Analog transition observed with an A/D converter. Analog voltage can be divided in 1024 = 210 parts at 10-bit resolution. : This refers to the difference between actual and logical values. This error is caused by offset errors, gain errors, non-linearity errors and noise. : Deviation of the line drawn between the zero transition point (00 0000 0000 00 0000 0001) and the full-scale transition point (11 1111 1110 11 1111 1111) for the device from actual conversion characteristics. : Deviation from ideal input voltage required to shift output code by one LSB.
Differential linearity error
Digital output 11 1111 1111 11 1111 1110 * * * * * * * * * * * 00 0000 0010 00 0000 0001 00 0000 0000 VOT VFST - VOT 1022 VNT - (1LSB x N + VOT ) 1LSB V(N + 1) T - VNT 1LSB (LSB) - 1 (LSB)
(1LSB x N + VOT)
Linearity error
Analog input VNT V(N + 1)T VFST
1LSB =
Linearity error =
Differential linearity error =
60
MB90660A Series
s EXAMPLES CHARACTERISTICS
(1) "H" Level Output Voltage (2) "L" Level Output Voltage
VOH - IOH VOH (V) 1.0 0.9 TA = +25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -2 -4 -6
VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V
-8 IOH (mA)
VOL (V) 1.0 0.9 TA = +25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 2
VOL - IOL
VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V
4
6
8 IOL (mA)
(3) "L" Level Output Voltage (P60 to P65)
(4) "H" Level Input Voltage/"L" Level Input Voltage
VIN (V) 5.0
VOL - IOL VOL (V) 1.0 0.9 TA = +25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 5 10 15
VIN - VCC (CMOS input)
TA = +25C
VCC = 2.7 V VCC = 3.0 V VCC = 3.5 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
20
25 IOL (mA)
0
2
3
4
5
6 VCC (V)
(5) "H" Level Input Voltage/"L" Level Input Voltage
V IN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 2
VIN - VCC (Hysteresis input)
TA = +25C
VIHS VILS
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
3
4
5
6 VCC (V)
(Continued)
61
MB90660A Series
(6) Power Supply Current (fcp = Internal frequency)
ICC (mA) 70 60 50 40 fCP = 8 MHz 30 20 10 0 3.0 4.0 5.0 6.0 VCC (V) I R (mA) 0.30 0 3.0 4.0 5.0 6.0 VCC (V) fCP = 4 MHz 5 10 fCP = 8 MHz fCP = 4 MHz fCP = 12.5 MHz 20 fCP = 16 MHz 15 fCP = 12.5 MHz
ICC - VCC
TA = +25C fCP = 16 MHz
ICCS (mA) 25
ICCS - VCC
TA = +25C
I A (mA) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0
IA - AVCC
TA = +25C fCP = 16 MHz
IR - AVR
TA = +25C fCP = 16 MHz
0.20
0.10
0 4.0 5.0 6.0 AV CC (V) 3.0 4.0 5.0 6.0 AVR (V)
(7) Pull-up Resistor
R (k) 1000
R - VCC
TA = +25C
100
10 2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0 VCC (V)
62
MB90660A Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
I S T N Z V C RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
63
MB90660A Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL:AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b
(Continued)
64
MB90660A Series
(Continued)
Symbol rel ear eam rlst Branch specification relative to PC Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension * Meaning
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note: The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
65
MB90660A Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing Listed in tables of instructions 1 2 1 1 2 2 0 0
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Note: "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles (b) byte Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) (c) word (d) long
Number Number Number Number Number Number of cycles of access of cycles of access of cycles of access +0 +0 +0 +1 +1 +1 1 1 1 1 1 1 +0 +0 +2 +1 +4 +4 1 1 2 1 2 2 +0 +0 +4 +2 +8 +8 2 2 4 2 4 4
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
66
MB90660A Series
Table 7 Mnemonic
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam
Transfer Instructions (Byte) [41 Instructions]
RG 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
#
2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+
~
3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a)
B
(b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b)
Operation
byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) (dir) (addr16) (Ri) (ear) (eam) (io) imm8 ((A)) ((RWi)+disp8) ((RLi)+disp8)
LH AH Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X - - - - - - - - - - - - - - - - - Z Z - - * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
STNZVC
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
67
MB90660A Series
Table 8 Mnemonic
MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 dir, A addr16, A SP, A RWi, A ear, A eam, A io, A @RWi+disp8, A @RLi+disp8, A RWi, ear RWi, eam ear, RWi eam, RWi RWi, #imm16 io, #imm16 ear, #imm16 eam, #imm16
Transfer Instructions (Word/Long Word) [38 Instructions] ~
3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 4 5+ (a) 3 4 5+ (a) RG 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0
#
2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+
B
(c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2x (c) 0 2x (c) 0 (d) 0 0 (d)
Operation
word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16 word (A) ((RWi) +disp8) word (A) ((RLi) +disp8) word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) word ((RWi) +disp8) (A) word ((RLi) +disp8) (A) word (RWi) (ear) word (RWi) (eam) word (ear) (RWi) word (eam) (RWi) word (RWi) imm16 word (io) imm16 word (ear) imm16 word (eam) imm16 word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A)
LH AH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
STNZVC
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW AL, AH /MOVW @A, T XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A, ear A, eam RWi, ear RWi, eam A, ear A, eam A, #imm32 ear, A eam, A
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
68
MB90660A Series
Table 9 Mnemonic
ADD A,#imm8 ADD A, dir ADD A, ear ADD A, eam ADD ear, A ADD eam, A ADDC A ADDC A, ear ADDC A, eam ADDDC A SUB A, #imm8 SUB A, dir SUB A, ear SUB A, eam SUB ear, A SUB eam, A SUBC A SUBC A, ear SUBC A, eam SUBDC A ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam A A, ear A, eam A, #imm16 ear, A eam, A A, ear A, eam A, ear A, eam A, #imm32 A, ear A, eam A, #imm32
Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] #
2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5
~
2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 6 7+ (a) 4 6 7+ (a) 4
RG 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
B
0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0
Operation
byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C) byte (A) (AH) + (AL) + (C) (decimal) byte (A) (A) -imm8 byte (A) (A) - (dir) byte (A) (A) - (ear) byte (A) (A) - (eam) byte (ear) (ear) - (A) byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) byte (A) (A) - (ear) - (C) byte (A) (A) - (eam) - (C) byte (A) (AH) - (AL) - (C) (decimal) word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32
LH AH Z Z Z Z - Z Z Z Z Z Z Z Z Z - - Z Z Z Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
STNZVC
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
RMW - - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
69
MB90660A Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~
RG
B
Operation
LH AH
I - - - - - - - - - - - -
S - - - - - - - - - - - -
T - - - - - - - - - - - -
N * * * * * * * * * * * *
Z * * * * * * * * * * * *
V * * * * * * * * * * * *
C - - - - - - - - - - - -
RMW
byte (ear) (ear) +1 0 2 2 2 2+ 5+ (a) 0 2x (b) byte (eam) (eam) +1 byte (ear) (ear) -1 0 2 3 2 2+ 5+ (a) 0 2x (b) byte (eam) (eam) -1 2 3 2 0 word (ear) (ear) +1 2+ 5+ (a) 0 2x (c) word (eam) (eam) +1 2 3 2 0 word (ear) (ear) -1 2+ 5+ (a) 0 2x (c) word (eam) (eam) -1 long (ear) (ear) +1 0 4 7 2 2+ 9+ (a) 0 2x (d) long (eam) (eam) +1 long (ear) (ear) -1 0 4 7 2 2+ 9+ (a) 0 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 A A, ear A, eam A, #imm16 A, ear A, eam A, #imm32 # Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32
LH AH
I - - - - - - - - - - -
S - - - - - - - - - - -
T - - - - - - - - - - -
N * * * * * * * * * * *
Z * * * * * * * * * * *
V * * * * * * * * * * *
C * * * * * * * * * * *
RMW
1 1 2 2 2+ 3+ (a) 2 2 1 1 2 2 2+ 3+ (a) 2 3
0 1 0 0 0 1 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
2 6 2 2+ 7+ (a) 0 5 3 0
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
70
MB90660A Series
Table 12 Mnemonic
DIVU DIVU DIVU DIVUW DIVUW MULU MULU MULU MULUW MULUW MULUW A A, ear A, eam A, ear A, eam A A, ear A, eam A A, ear A, eam
Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] #
1 2 2+ 2 2+ 1 2 2+ 1 2 2+
~
* * * * *
1 2 3 4 5
RG 0 1 0 1 0 0 1 0 0 1 0
B
0 0 *
6
Operation
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) long (A)/word (ear) Quotient word (A) Remainder word (ear) long (A)/word (eam) Quotient word (A) Remainder word (eam)
LH AH - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - -
S
- - - - - - - - - - -
T
- - - - - - - - - - -
N
- - - - - - - - - - -
Z
- - - - - - - - - - -
V
* * * * * - - - - - -
C
* * * * * - - - - - -
RMW - - - - - - - - - - -
0 *
7
*8 *9 *10 *11 *12 *13
0 0 byte (AH) *byte (AL) word (A) (b) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) (c) word (A) *word (ear) long (A) word (A) *word (eam) long (A)
*1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
71
MB90660A Series
Table 13 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B
Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A)
LH AH
I - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
T - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
N * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Z * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
V R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
RMW
2 2 3 2 2+ 4+ (a) 3 2 2+ 5+ (a) 2 2 3 2 2+ 4+ (a) 3 2 2+ 5+ (a) 2 2 3 2 2+ 4+ (a) 3 2 2+ 5+ (a)
0 0 0 1 (b) 0 0 2 0 2x (b) 0 0 0 1 (b) 0 0 2 0 2x (b) 0 0 0 1 (b) 0 0 2 0 2x (b)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
byte (A) not (A) 0 0 2 1 byte (ear) not (ear) 0 2 3 2 2+ 5+ (a) 0 2x (b) byte (eam) not (eam) 0 0 0 0 0 1 (c) 0 0 2 0 2x (c) 0 0 0 0 0 1 (c) 0 0 2 0 2x (c) 0 0 0 0 0 1 (c) 0 0 2 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A 2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A 2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A
NOTW A NOTW ear NOTW eam
word (A) not (A) 0 0 2 1 word (ear) not (ear) 0 2 3 2 2+ 5+ (a) 0 2x (c) word (eam) not (eam)
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
72
MB90660A Series
Table 14 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # ~ Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH AH
I - - - - - -
S - - - - - -
T - - - - - -
N * * * * * *
Z * * * * * *
V R R R R R R
C - - - - - -
RMW
2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0 2 6 2 2+ 7+ (a) 0
- - - - - -
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Table 15 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A)
LH AH
I - - - - - -
S - - - - - -
T - - - - - -
N * * * * * *
Z * * * * * *
V * * * * * *
C * * * * * *
RMW
0
X - - - - -
- - - - - -
- - * - - *
byte (ear) 0 - (ear) 0 2 3 2 2+ 5+ (a) 0 2x (b) byte (eam) 0 - (eam) 1 2 0 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
word (ear) 0 - (ear) 0 2 3 2 2+ 5+ (a) 0 2x (c) word (eam) 0 - (eam)
Table 16 Mnemonic NRML A, R0 # 2 ~ *1
RG
Normalize Instruction (Long Word) [1 Instruction] B 0 Operation
long (A) Shift until first digit is byte (R0) Current shift count LH AH
I -
S -
T -
N -
Z *
V -
C -
RMW
1
"1" -
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
73
MB90660A Series
Table 17 Mnemonic
RORC A ROLC A RORC RORC ROLC ROLC ASR LSR LSL ear eam ear eam A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions] B
0 0 0 2x (b) 0 2x (b) 0 0 0 0 0 0 0 0 0 0 0 0
#
2 2
~
2 2
RG 0 0 2 0 2 0 1 1 1 0 0 0 1 1 1 1 1 1
Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit) word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit) word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Arithmetic right shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
LH AH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - -
STNZVC
- - - - - - - - - - - - - - - - - - - - - - - - * * - * * - * * - * * - * * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * *
RMW
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
74
MB90660A Series
Table 18 Mnemonic
BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP CALLP CALLP rel rel rel rel
Branch 1 Instructions [31 Instructions] Operation
Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0 Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0 Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam) word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2) word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15 (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15 (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23 LH AH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4
~
* *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10
1
RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c)
I
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
STNZVC
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
RMW
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24 @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 @eam *6 addr24 *7
*1: *2: *3: *4: *5: *6: *7:
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
75
MB90660A Series
Table 19 Mnemonic
CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE CBNE CWBNE CWBNE DBNZ DBNZ DWBNZ DWBNZ INT INT INTP INT9 RETI LINK ear, #imm8, rel eam, #imm8, rel*9 ear, #imm16, rel eam, #imm16, rel*9 ear, rel eam, rel ear, rel eam, rel #vct8 addr16 addr24
Branch 2 Instructions [19 Instructions] B
0 0 0 (b) 0 (c) 0
#
3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2
~
* *1 *2 *3 *4 *3 *5 *
6 1
RG 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0
Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - R R R R * -
S
- - - - - - - - - - S S S S * -
T
- - - - - - - - - - - - - - * -
N
* * * * * * * * * * - - - - * -
Z
* * * * * * * * * * - - - - * -
V
* * * * * * * * * * - - - - * -
C
* * * * * * - - - - - - - - * -
RMW
- - - - - - - * - * - - - - - -
Branch when byte (ear) = (ear) - 1, and (ear) 0 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) 6x (c) (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
*5 *6 20 16 17 20 15 6
#local8
UNLINK RET *7 RETP *8
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
*1: *2: *3: *4: *5: *6: *7: *8: *9:
5 when branching, 4 when not branching 13 when branching, 12 when not branching 7 + (a) when branching, 6 + (a) when not branching 8 when branching, 7 when not branching 7 when branching, 6 when not branching 8 + (a) when branching, 7 + (a) when not branching Retrieve (word) from stack Retrieve (long word) from stack In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode.
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
76
MB90660A Series
Table 20 Mnemonic
PUSHW PUSHW PUSHW PUSHW POPW POPW POPW POPW JCTX AND OR A AH PS rlst A AH PS rlst @A CCR, #imm8 CCR, #imm8
Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~
4 4 4 *3 3 3 4 *2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 *1 1 1 1 1 1 1 1 1 RG 0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
#
1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1
B
(c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LH AH - - - - - - - - - - - - - - - - - - - Z - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - -
I
- - - - - - * - * * * - - - - - - - - - - - - - - - - -
STNZVC
- - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - -
RMW - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte (CCR) (CCR) and imm8 byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank
MOV RP #imm8 , MOV ILM, #imm8 MOVEA RWi, ear MOVEA RWi, eam MOVEA A, ear MOVEA A, eam ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
77
MB90660A Series
Table 21 Mnemonic
MOVB MOVB MOVB MOVB MOVB MOVB SETB SETB SETB CLRB CLRB CLRB BBC BBC BBC BBS BBS BBS SBBS WBTS WBTC A, dir:bp A, addr16:bp A, io:bp dir:bp, A addr16:bp, A io:bp, A dir:bp addr16:bp io:bp dir:bp addr16:bp io:bp dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel addr16:bp, rel io:bp io:bp
Bit Manipulation Instructions [21 Instructions] B
(b) (b) (b)
#
3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3
~
5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Operation
byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH Z Z Z - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - -
I
- - - - - - - - - - - - - - - - - - - - -
STNZVC
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
RMW - - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
2x (b) Branch when (addr16:bp) b = 1, bit = 1 - * *
5 5
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
- -
*1: *2: *3: *4: *5:
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
78
MB90660A Series
Table 22 Mnemonic SWAP SWAPW/XCHW AL, AH EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1
RG
B 0 0 0 0 0 0
Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension
LH AH
I - - - - - -
S - - - - - -
T - - - - - -
N - - * * R R
Z - - * * * *
V - - - - - -
C - - - - - -
RMW
0 0 0 0 0 0
- - X - Z -
- * - X - Z
- - - - - -
Table 23 Mnemonic
MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI MOVSW/MOVSWI MOVSWD SCWEQ/SCWEQI SCWEQD FILSW/FILSWI
String Instructions [10 Instructions] Operation
LH AH - - - - - - - - - - - - - - - - - - - -
#
2 2 2 2 2 2 2 2 2 2
~
* *2 *1 *1 6m +6 * *2 *1 *1 6m +6
2 2
RG * *5 *5 *5 *5 * *8 *8 *8 *8
8 5
B
3
I
- - - - - - - - - -
S
- - - - - - - - - -
T
- - - - - - - - - -
N
- - * * * - - * * *
Z
- - * * * - - * * *
V
- - * * - - - * * -
C
- - * * - - - * * -
RMW - - - - - - - - - -
* Byte transfer @AH+ @AL+, counter = RW0 *3 Byte transfer @AH- @AL-, counter = RW0 *4 Byte retrieval (@AH+) - AL, counter = RW0 *4 Byte retrieval (@AH-) - AL, counter = RW0 *3 Byte filling @AH+ AL, counter = RW0 * Word transfer @AH+ @AL+, counter = RW0 *6 Word transfer @AH- @AL-, counter = RW0
6
*7 Word retrieval (@AH+) - AL, counter = RW0 *7 Word retrieval (@AH-) - AL, counter = RW0 *6 Word filling @AH+ AL, counter = RW0
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
79
MB90660A Series
s MASK OPTION LIST
Part number No. Specifying procedure P00 to P07 P10 to P17 P20 to P27 P30 to P33 P40 to P47 P60 to P66 RST DTTI MD2 2 MD1 MD0
Accept asynchronous reset input
MB60662A MB90663A Specify when ordering masking
MB90P663A Set with EPROM programmer
1
Pull-up resistor can be selected for each pin
Pull-up resistor can be selected for each pin
Pull-down resistor Pull-up resistor Pull-up resistor Can be selected all at once
Cannot be selected; pull-down resistor not provided Pull-up resistor Pull-up resistor Can be selected all at once
3 Accepted Not accepted
Can be selected
Can be selected
Notes: * A specification of "yes" for accept asynchronous reset input refers to a function whereby reset input is accepted when oscillation for output ports (including peripheral resource output) is stopped and port output (including peripheral resource output) is forced Hi-z. Note, however, that since internal reset (reset of the CPU and peripheral resources) is synchronized with the clock, the CPU and peripheral resources are not initialized when the clock is stopped. * For details on writing to the MB90P663A, see Chapter 6, "s PROGRAMMING THE MB90P663A EPROM". * Use of a pull-up/pull-down resistors for the mode pins (MD2 to MD0) can be selected separately for each pin. If "yes" is selected, a pull-up is attached to MD0 and MD1 and a pull-down to MD2 for mask ROM versions. A pull-up is attached to MD0 and MD1, but a pull-down is not attached to MD2 for OTP versions. * Since it takes eight machine cycles to make option settings for the MB90P663A, options cannot be set between when power is first turned on and the clock is supplied. (This results in a setting of no pull-up for all pins and accept asynchronous reset input.)
80
MB90660A Series
s ORDERING INFORMATION
Part number MB90662AP-SH MB90663AP-SH MB90P663AP-SH MB90662APFM MB90663APFM MB90P663APFM Package 64-pin plastic SH-DIP (DIP-64P-M01) Remarks
64-pin plastic LQFP (FTP-64P-M09)
81
MB90660A Series
s PACKAGE DIMENSIONS
64-pin Plastic SH-DIP (DIP-64P-M01)
58.00 -0.55 +.008 2.283 -.022
+0.22
INDEX-1 INDEX-2
17.000.25 (.669.010)
5.65(.222)MAX 3.00(.118)MIN 1.00 -0 +.020 .039 -0 1.7780.18 (.070.007) 1.778(.070) MAX 55.118(2.170)REF
+0.50
0.250.05 (.010.002) 0.450.10 (.018.004) 0.51(.020)MIN 15MAX 19.05(.750) TYP
C
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions in mm (inches)
64-pin Plastic LQFP (FPT-64P-M09)
14.000.20(.551.008)SQ
48
12.000.10(.472.004)SQ
33
1.50 -0.10 +.008 .059 -.004
+0.20
49
32
9.75 (.384) REF 1 PIN INDEX
13.00 (.512) NOM
64
17
LEAD No.
1
16
Details of "A" part "A"
M
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
0.127 -0.02 +.002 .005 -.001
+0.05
0.100.10 (STAND OFF) (.004.004)
0.10(.004) 0 10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F64018S-1C-2
Dimensions in mm (inches)
82
MB90660A Series
MEMO
83
MB90660A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED Printed in Japan
84
*DS07-13604

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